1. Field of the Invention
This invention relates to circuitry for the distribution of clock timing signals within integrated circuits and more particularly to clock timing signal distribution circuitry within integrated circuits such as synchronous dynamic random access memories (SDRAM) that must provide multiple clock phases with minimal skew in relation to an external system clock.
2. Description of Related Art
As shown in FIG. 1 and is well known in the art, an SDRAM will have multiple cell arrays within multiple memory banks to retain digital data. The system Address Bus A.sub.0, A.sub.1, . . . , A.sub.n will be connected to the Address Buffer to receive the address of the location of the retained digital data within the multiple cell arrays of the multiple memory banks. The Address Buffer will transfer the requested address to the appropriate cell array within a selected memory bank, where the row and column address decoders will select the appropriate location of the digital data.
The chip select CS, the row address strobe RAS, column address strobe CAS, and the write enable WE signals will form a command bus and will be received by the command decoder. These signals will be decoded and transferred to the control signal generator. The control signal generator will generate and transfer a set of control signals that will determine the operation modes of the selected cell array in the one memory bank. These modes will be variations and combinations of fetching or reading from, storing or writing to, or refreshing of the digital data within the cell arrays of the memory banks.
The data control circuitry will receive data from the data input/output buffers which in turn are connected to a system data bus to receive and transmit the digital data DQ.sub.0, . . . , Dq.sub.x to and from the cell arrays within the memory banks.
The external system clock XCLK will be transferred to the clock buffer. The clock buffer will then transfer the clock to the other operating units of the SDRAM. The clock that controls the timings of the data control circuitry must be such that the digital data DQ.sub.0, . . . , Dq.sub.x will be appropriately aligned with the external system clock XCLK.
During periods of inactivity for an SDRAM, it is desirable that the SDRAM be deactivated. This will be controlled by the clock enable signal XCKE.
The structure and timing of the clock distribution within the SDRAM is described in "A 2.5 ns Clock Access 250 Mhz, 256 Mb SDRAM with Synchronous Mirror Delay" by T. Saeki et al, IEEE Journal of Solid State Circuits, Vol 31 No. 11 November 1996, pp 1656-1664, and shown in FIGS. 2a and 2b. The external system clock XCLK is received by the input buffer IBUF. The input buffer IBUF has a delay time from the input of the external system clock XCLK to the output of the input buffer IBUF that is designated d1. The output of the input buffer IBUF is the input to multiple internal buffers INTBUF. The internal buffers INTBUF will then transfer the internal clock ICLK to the functional units within the SDRAM. The delay time for the internal buffer INTBUF is designated d2.
The command signals chip select CS, the row address strobe RAS, column address strobe CAS, and the write enable WE, as well as the address bus A.sub.0, A.sub.1, . . . , A.sub.n will be gated into the SDRAM during the rise of the internal clock ICLK from a first logic level (0) to a second logic level (1). The internal clock ICLK will be the timing signal that is used to synchronize the transfer of the digital data from the cell array in the memory banks to the data input/output buffers and to the data bus DQ.sub.0, . . . , Dq.sub.x. The internal clock ICLK will be delayed or skewed by the delay d1 of the input buffer IBUF plus the internal buffer INTBUF. Since the timing of the functions of the SDRAM are determined by the internal clock ICLK, the access time T.sub.acc of the fetching or reading of the digital data can be no smaller than the clock skew d1+d2 plus the period of the internal clock ICLK. This forces the minimum time that data can be cycled from the SDRAM to be two external system clock XCLK periods. As computer system clocks are approaching transfer rates of 100 Mhz, it is desirable that the access time T.sub.acc of an SDRAM to be brought to one cycle of the external system clock XCLK. This means that the clock skew d1+d2 must be eliminated from the clock distribution system.
Phase Locked Loops (PLL) and Delay Locked Loops (DLL) are well known in the art for synchronizing two timing signals. In both cases the time to achieve synchronization or lock may be on the order of 50 cycles or more. With such long lock times in SDRAM applications, the internal clocking signals ICLK can not be deactivated during the periods that the SDRAM is inactive. This will increase the power dissipation of the SDRAM to undesirable levels.
The Clock Synchronization Delay (CSD) is a class of synchronizing circuits that will eliminate the clock skew d1+d2 within two clock cycles. two types of CSD's known in the art are the latched type CSD and the nonlatched synchronous mirror delay SMD.
FIGS. 3a and 3b show a schematic diagram and a timing diagram for the general structure of a CSD circuit. As in FIG. 2a, the external system clock XCLK is received by the input buffer IBUF. The output IBO of the input buffer IBUF is delayed by the delay d1. The output IBO of the input buffer IBUF is the input to the delay monitor circuit DMC. The delay monitor circuit DMC will provide an output that is a delayed input signal IBO by a fixed amount that is usually the sum of the delay d1 of the input buffer IBUF and the delay d2 of the internal buffer INTBUF.
The output of the delay monitor circuit DMC will be the input of the forward delay array FDA. The forward delay array FDA comprises a number of delay elements that will each delay the input of the forward delay array FDA by an increment of time t.sub.df. The output of each delay element of the forward delay array FDA is the input for each subsequent delay element and is also one of the multiple outputs of the forward delay array FDA.
The multiple outputs of the forward delay array FDA are inputs to the mirror control circuit MCC. The output IBO of the input buffer circuit IBUF is also provided to multiple inputs of the mirror control circuit MCC. The output IBO of the input buffer circuit IBUF is compared with each output of the forward delay array FDA. When one of the outputs of the forward delay array FDA is aligned with the n+1 pulse of the output IBO of the input buffer IBUF, the mirror control circuit will transfer that one output to the backward delay array BDA. The mirror control circuit MCC will have multiple outputs to transfer any one of the inputs of the mirror control circuit MCC from the forward delay array FDA to the backward delay array BDA. The backward delay array BDA is comprised of multiple delay elements. Each delay element has a delay time t.sub.df equal to the delay time of the forward delay array FDA.
The delayed clock pulse will be delayed by a factor of: EQU .tau..sub.FDA =.tau..sub.ck -(d.sub.1+ d.sub.2)
where
.tau..sub.ck is the time of the period of the external clock. PA2 .tau..sub.FDA is the time of the period of the external clock less the skew d.sub.1 +d.sub.2.
The delayed clock pulse will be further delayed by the factor .tau..sub.FDA in the backward delay array BDA. thus the nth pulse output of the backward delay array BDA will be delayed by a factor of EQU 2d.sub.1 +d.sub.2 +2(.tau..sub.ck -d.sub.1 +d.sub.2)
This will make the nth pulse of the backward delay array BDA misaligned with the n+2 pulse of the external system clock XCLK by a factor of the delay d.sub.2 of the internal buffer INTBUF.
The output of the backward delay array BDA will be the input of the internal buffer INTBUF. The nth internal clock ICLK will now be aligned with the system clock XCLK.
If the system clock CLK is disabled by the clock enable CLKE of FIG. 1 and the re-enabled, it will require only two system clock cycles for the internal clock ICLK to align with the system clock XCLK. Thus any data can be accessed within a single period .tau..sub.ck of the system clock XCLK.
The mirror control circuit MCC will be of two types. The first type as described in "Capacitive Coupled Bus with Negative Delay Circuit for High Speed and Low Power (10 GB/s&lt;500 mw) Synchronous DRAM) by T. Yamada et al, Digest of Papers for IEEE Symposium on VLSI Circuits; 1996, pp 112-113, will be a latch that will fix the delay segment of the forward delay element FDA selected to be transferred to the backward delay array BDA. Once the latch is set, it will only be reset during the inactivity time of the SDRAM. Upon reactivation of the SDRAM, the decision of the length of the delay necessary will be recreated.
The second type of mirror control circuit MCC will be the synchronous mirror delay. The mirror control circuit MCC will be a pass gate that is activated when the output of the forward delay circuit FDA is aligned with the n+1 pulse of the output IBO of the input buffer circuit IBUF. The synchronous mirror delay will chose on each cycle of the system clock XCLK, which of the delay elements is satisfactory to align with the output IBO of the input buffer circuit IBUF.
As the system timing requirements of modern computers has increased, it is now necessary to double the frequency of transfer of data from SDRAM, that is to transfer data from the data bus to the system twice every clock cycle.
A new class of SDRAM is referred to as a Double Data Rate (DDR) SDRAM. The specification of the DDR SDRAM does not specify that the external system clock XCLK have a precise 50% duty cycle. However, it must have the first data present at the Data Input/Output Buffers at the beginning of a clock cycle, that is when the external system clock XCLK rises from the first logic level (0) to the second logic level (1). The second data must be present at the Data Input/Output Buffers at the time that is one half of the period of the system clock .tau..sub.ck or to be 180.degree. out of phase with the system clock XCLK.
This creates a requirement for a dual phase clock having a precise 50% duty cycle. The dual phase clock must be deskewed with respect to the external system clock XCLK in the two cycles from the clock enable signal XCKE.
U.S. Pat. No. 5,663,767 (Rumreich et al.) describes a clock retiming apparatus for aligning a video clock edge with horizontal synchronization signal of a video signal by using latched outputs of delay lines. The outputs of the delay lines are selected according to their alignment with the horizontal synchronization signal.
U.S. Pat. No. 5,489,864 (Ashuri) discloses an integrated circuit for deskewing and adjusting a delay of a synthesized waveform. The synthesized waveform is initially produced by a digital-to-time domain converter which is coupled to a synchronous delay line and a pattern ROM though a shifter and pattern register. The synchronous delay line generates a plurality of taps in response to a reference signal. Each one of the taps has a unit delay and is coupled to the digital to time domain converter. The integrated circuit described comprises a microdelay calibration circuit, deskew control circuit, and a delay interpolation circuit. The microdelay calibration circuit is coupled to the synchronous delay line and the deskew control circuit. The deskew control circuit is further coupled to the shifter and the delay interpolation circuit. The delay interpolation circuit receives the output of the digital-to-time domain converter and outputs a deskewed synthesized waveform.